A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.