Wafer Level Batch Fabrication of Silicon Microchannel Heat Sink and Electrical Through-Silicon Vias for 3D ICs

Cooling and power delivery are among the key challenges in three dimensional (3D) integration of high-performance ICs. We investigate various CMOS compatible approaches to integrate microchannel heat sinks and through-silicon vias (TSVs) to enable fluidic and electrical interconnections in a 3D stack of ICs. Microchannels are etched and capped using low temperature processes such as adhesive bonding or silicon-to-silicon (Si-Si) direct bonding techniques. After thinning the capping layer, TSVs are etched in the fins of the parallel microfluidic cooling channels. Using the mesh process discussed in the paper, the pinch off time for TSVs is reduced. Subsequently, high aspect ratio (10:1) TSVs are filled with copper using

bottom up electroplating process. Solder bumps and polymer pipes can be used for electrical interconnections as well as fluid inlet/outlet ports to the substrate. Potential trade-offs that have to be considered while integrating electrical and fluidic interconnects in a wafer are also described in the paper.