Vertical Gate‐All‐Around MOSFETs With Nominally Symmetric Source and Drain Structures for Logic‐Function Emulation

ABSTRACT

Vertical gate‐all‐around (VGAA) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs), with superior electrostatic control and potential in vertical integration, have become promising candidates for sub‐3 nm integrated circuit scaling. Nevertheless, practical implementations of VGAA MOSFETs typically suffer from source‐drain (S‐D) asymmetry arising from bottom‐up fabrication processes, resulting in configuration‐dependent electrical behavior and limited circuit‐level symmetry. This study reports the fabrication and electrical characterization of proof‐of‐concept VGAA MOSFETs with nominally symmetric S and D structures. An integrated spacer‐sacrificial layer strategy is developed to enable the simultaneous formation of the source and drain, thereby establishing nominal structural symmetry between them. The device exhibits similar electrical characteristics upon S/D interchange, with relative I _on differences of 10%–20% and V _th differences of 0.04–0.16 V. Mechanism analysis reveals that the device performance is primarily limited by contact barriers, providing guidance for further optimization. Moreover, the synergistic gate‐drain modulation observed in the present devices enables the emulation of logic functions at the single‐device level. This study lays a foundation for the future implementation of symmetric VGAA MOSFETs in next‐generation 3D integrated circuits.