Underfill Selection for Flip Chip BGA Warpage Control

Flip chip packages are becoming more popular

due to many factors such as electrical performance,

functionality and high I/O interconnections. To fulfill

such needs in different applications, chip sizes are

gradually becoming larger. Due to the large die sizes

with high pin count, small bump pitch and low-K

inter-metal-dielectric material, reliability concerns

are arising at the interfaces of die, solder bumps and

substrate. Of concern are package warpage issues,

bump cracks, underfill void/delamination/cracks and

die cracks, etc. The reliability issues can be solved

by selecting more appropriate underfill materials to

relief mechanical stress from CTE mismatch. Many

commercial brands of underfill materials are

available in the market and the underfill properties

such as Tg, modulus, CTE, viscosity, flow

characteristics, and adhesion need to be characterized

before implementation. In this project, the underfill

properties are studied and discussed and stress

modeling for large dice in large packages is

performed. Package data such as warpage, bump

crack and delamination are measured for verification.

The optimum underfill material for large die flip chip

packages has been implemented in mass production.