DOI: 10.1021/acsaelm.6c00902 ISSN: 2637-6113

Synergistic Engineering of Organic Ferroelectric Gate Insulators and Oxide Bilayer Channels for Synaptic Transistors with High Linearity and Wide Dynamic Range

Ji-Won Jang, Hyun-Sik Kim, Hong-Sub Lee, Sung-Min Yoon

Abstracts

Ferroelectric synaptic transistors employing organic ferroelectric copolymer poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulators and InGaZnO (IGZO)-based oxide semiconductor channel layers were fabricated and characterized to address the fundamental challenge of nonlinear conductance modulation arising from abrupt polarization reversal in ferroelectric-based synaptic devices. P(VDF-TrFE) layers with thicknesses of 150, 200, and 380 nm were analyzed using the Kolmogorov–Avrami–Ishibashi (KAI) model and Merz’s law. This analysis revealed that decreasing the GI thickness increases the activation electric field (EA), promoting more gradual polarization reversal. However, the elevated EA also imposed limitations on the extent of complete polarization reversal, consequently resulting in a reduced dynamic range. To overcome this limitation, an IGZO/In2O3 bilayer channel structure was introduced, in which the In2O3 layer elevated the effective carrier density through its higher oxygen vacancy concentration and lower conduction band minimum than IGZO, thereby raising the conductance saturation point and expanding the dynamic range. The optimized device achieved a linearity parameter β of 0.95, a dynamic range of 5.2, and a paired-pulse facilitation (PPF) index of approximately 210% at a pulse interval of 20 μs, representing improvements of 7.6, 68, and 20%, respectively, over the single-layer channel device with a 150-nm-thick GI. These results demonstrate that the synergistic combination of EA control through GI engineering and conductance window expansion via channel engineering provides an effective strategy for simultaneously optimizing linearity and dynamic range in ferroelectric synaptic transistors, thus providing a framework for the development of high-performance neuromorphic hardware.