StEdge: A Low-Power Real-Time Hardware Accelerator for Edge Detection Using Stochastic Computing

Edge detection is a fundamental operation in real-time image and video processing systems. However, conventional gradient-based hardware implementations incur significant power, area, and computational overheads. This work presents StEdge, a low-power, configurable hardware accelerator for real-time edge detection based on stochastic computing (SC), supporting both Sobel and Prewitt gradient operators within a unified architecture. The proposed design reformulates gradient computation in the stochastic domain, replacing arithmetic-intensive operations with lightweight logic gates. To further reduce hardware complexity, a deterministic concatenation-based accumulation strategy is introduced that preserves the expected probabilistic behavior of stochastic addition while eliminating the multiplexer and stochastic select-line circuitry required by conventional SC implementations. The architecture is implemented on a Basys 3 FPGA and integrated with an OV7670 camera to demonstrate real-time edge detection at 30 fps. Edge detection quality is evaluated on the BSD500 benchmark dataset against human-annotated ground truth using Precision, Recall, F-score, PR-AUC, and Pratt’s Figure of Merit. The stochastic Sobel detector retains more than 80% of the score of its deterministic counterpart on every metric, and the stochastic Prewitt detector retains between 57% and 77%. On the FPGA, the proposed design reduces slice LUT usage by 11.6% and total on-chip power by 17% relative to a traditional Sobel implementation on the same platform. ASIC synthesis with Synopsys Design Compiler targeting the ASAP7 7 nm library reduces compute-core area by up to 26% and power by up to 28% at a 1 GHz target frequency. These results show that stochastic computing is an effective option for real-time edge detection in resource-constrained embedded vision systems.