SLM-Arch: Trade-off Analysis and Optimized Hardware Design for Small Language Models

Small language models (SLMs) are increasingly deployed in resource-constrained environments, motivating the development of specialized accelerators. However, designing efficient SLM accelerators remains challenging due to diverse application requirements and complex interplay among architectural parameters and workload characteristics. This paper proposes a closed-form analytical model that accurately evaluates latency and energy consumption for SLM accelerators across different dataflows and technology nodes (e.g., 28 nm CMOS and 7 nm FinFET). The model accounts for repeated data accesses, inter-processing element (PE) interconnections, and the energy costs of different DRAM operations, resulting in high simulation accuracy. Validation results show an average accuracy of \(96.0\% \) for latency, \(96.8\% \) for PE array energy, and \(97.1\% \) for DRAM energy. Using the proposed model, we conduct extensive design space exploration (DSE) and derive empirical formulas for optimized PE array sizes, along with analytical methods for memory capacities that minimize redundant memory accesses. We also examine optimized combinations of PE array size, memory capacity, bandwidth, and dataflow. Furthermore, we investigate area-constrained scenarios (2 mm ² , 7 mm ² , 30 mm ² ) and provide guidelines for allocating computation and memory resources. Results show that the optimized PE array size is around 240 × 240 for IS and OS, while WS requires at least 300 × 300, but with lower memory demands. Under relaxed area constraints, at least 30 GB/s of bandwidth is needed for full area utilization, whereas strict area limits favor maximizing the PE array. Overall, this work provides practical guidelines for hardware parameter selection, enabling optimized SLM accelerator deployment across diverse applications.