Simulated On-Board AI-Based Classification of Radiation-Induced SRAM Event Upsets

Radiation monitoring with SRAM-based FPGAs traditionally relies on offset-histogram analysis, which requires a chip-specific calibration campaign at an accelerator before multiple-cell upsets (MCUs) can be discriminated from coincident single-cell upsets (SCUs). The cost and complexity of such calibration restrict the approach to dedicated, beam-test-funded programs. We propose an AI-based on-board classifier that achieves MCU/SCU discrimination directly, without any chip-specific calibration. A lightweight Multi-Layer Perceptron (MLP), trained entirely on synthetic data covering five representative bit-interleaving layouts, is integrated on an AMD Artix-7 XC7A200T FPGA together with per-detection-element telemetry aggregation. The classifier achieves F1 = 0.92–0.97 on structured BRAM layouts when per-chip calibration data are available (calibrated ceiling) and, without any chip-specific calibration, retains F1 up to 0.81 ± 0.02 (held-out, mean over five seeds) on previously unseen layouts with near-perfect recall. A sensitivity analysis across a 20× range of SEU rates and a 4× range of MCU fractions confirms the robustness of the proposed approach. A feature-ablation study identifies an indispensable feature subset, while a comparative evaluation of four alternative classifier architectures (decision tree, support vector machine (SVM), two MLP variants) establishes the reference MLP as the optimal choice. Post-implementation results on the Artix-7 200T show that the MLP-enhanced and calibrated-histogram designs occupy nearly identical FPGA footprints, reframing the choice between them as an operational decision driven by calibration availability rather than by hardware cost.