Sequential-Access-Aware Cell-Split-Mapped and Column-Selective MLC STT-MRAM for an Area and Energy-Efficient Viterbi Decoder Design

Modern low-power wireless communication systems often operate under strict energy and area constraints, especially in edge and embedded platforms. This paper proposes novel optimization techniques for Multi-Level-Cell STT-MRAM (MLC STT-MRAM), replacing SRAM for an area- and energy-efficient Viterbi decoder in wireless communication. Three key techniques are introduced to mitigate the performance and energy consumption overhead of MLC STT-MRAM while preserving its high area efficiency. First, the energy barrier optimization technique is proposed, leveraging the fact that the survivor memory of the Viterbi decoder does not need to hold its data for a long period. This optimization significantly reduces the write energy. Second, the sequential-access-aware cell-split-mapping (SAA CSM) method exploits the sequential memory write and read access patterns of the Viterbi decoder, enabling a one-step write. Third, the column selective read technique utilizes column multiplexers within the memory peripheral circuits, eliminating unnecessary read operations and their associated circuits, thereby reducing power consumption and area. The proposed Viterbi decoder, compatible with IEEE 802.11n/ac, is implemented in a 28-nm CMOS technology, achieving 17.24% area and 55.15% energy reduction compared with a conventional MLC STT-MRAM-based design. Even compared with the conventional 6T SRAM-based design, proposed design achieves 51.94% and 9.09% reduction in area and energy consumption, respectively, without performance degradation.