Selective Plasma Mode Modulation in HfO2 Charge Trap Layers via RP/DP/RP Atomic Layer Deposition for Enhanced Memory Performance and Interface Quality

Hafnium oxide (HfO2) has emerged as a promising charge trap layer (CTL) for nonvolatile memory devices; however, its long-term reliability remains challenging due to leakage current through grain boundary pathways and interface defect formation. Within plasma-enhanced atomic layer deposition (PEALD), direct plasma ALD (DPALD) forms crystalline HfO2 with deeper trap sites, while its ion-assisted nature may contribute to interface damage, resulting in a lower net trap density than remote plasma ALD (RPALD), which better preserves interfacial quality. We propose an interface–bulk–interface (RP/DP/RP) process design that places RPALD at the interfaces and DPALD in the bulk, aiming to combine bulk trap sites with interfacial protection. Charge trap memory (CTM) devices were fabricated across RP/DP/RP thickness combinations. Within the tested range, the optimized structure exhibited the widest memory window and the highest effective trapped charge density among the measured devices, improving upon DPALD and comparable to RPALD, together with the lowest near-interface trap density at the Si/Al2O3 interface. The device also maintained a stable memory window up to 104 program/erase cycles, and short-term retention data suggest potentially stable program and erase states, requiring longer-term validation. These results indicate that spatial modulation of plasma modes offers a process-level strategy for improving HfO2-based CTM devices.