Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack

Cryptography is essential to ensure data security in embedded devices that handle sensitive data. SRAM boosts overall performance by temporarily storing cryptographic keys. However, attackers can use side-channel, such as Power Analysis, to exploit power consumption patterns and extract secret keys. Once a key is compromised, encrypted data becomes vulnerable. There are many secure SRAM cell designs available in the literature, but they often degrade other performance parameters. This paper presents a novel 10-T SRAM cell design that provides protection against power analysis side-channel attacks (SCA) across all three cell operations, while also maintaining the performance of other key parameters. Monte Carlo simulations were conducted on 1000 samples each for case when BL=Q and BL≠Q during reading, writing, and holding data, using Cadence Virtuoso with a 45 nm technology node at 1V/270°C. Based on these simulations, the mean power difference was evaluated. The proposed P-10T SRAM cell exhibits a 0% mean power difference in all three modes of operation, demonstrating complete resilience to power analysis SCA. The design achieves 84.87% reliability with hold stability, read stability, and write ability values of 429 mV, 242 mV, and 250 mV, respectively. Furthermore, the write power dissipation of P-10T cell is 57.44 μW, which is 1.80 × lower than the power consumed by the conventional 6T cell.