MMzk ‐ D128 : A High‐Throughput DMA ‐128‐Aware 384‐Bit Montgomery Multiplier on SoC FPGA Hikaru Okamoto, Vu Trung Duong Le, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima

ABSTRACT

Montgomery multiplication is a dominant kernel in zk‐SNARK multiscalar multiplication, and sustained throughput on an edge SoC FPGA depends on both arithmetic efficiency and data delivery. This paper presents

, a DMA128‐aware 384‐bit Montgomery multiplier that preserves the inherited 146‐cycle CIOS core and redesigns the surrounding system through DMA128‐aware BRAM organization, two‐level double buffering, BRAM‐to‐core scheduling, and bandwidth‐aware multicore sizing. The analytical model retains 85 cases per half‐buffer under the same BRAM‐bit budget and selects an 11‐core DMA128 configuration. We implemented the complete 11‐core configuration and a six‐core DMA64/DMA128 A/B pair on the same KV260; the DMA64 reference operates at 175.04 MHz and the DMA128 designs at 180.47 MHz. Measured throughput increases from 2.27 to 2.644 Gbps in the six‐core A/B experiment (1.16×), while the 11‐core implementation reaches 4.792 Gbps. Its hardware counter reports 1225 cycles for the 85‐case batch, 1.41% above the 1208‐cycle analytical prediction. The postimplementation 11‐core system uses 48,903 LUTs, 31,052 FFs, 176 DSPs, and 11 BRAM36 blocks. Matched INA260 idle and active measurements of 3.470 and 4.768 W give 1.298 W workload‐induced board power and an EDP of 83.34  for the 100 K‐operation workload. The FPGA and CPU EDP rows consistently use workload‐induced dynamic power.