Scalable Density Advancement in Embedded Bridge Interposers through Adaptive Patterning® and Adaptive Pad Stacks

The ubiquitous use of AI in every aspect of modern life has driven the semiconductor industry to further advance AI and advanced packaging. This has led to increasing demand for high-density interposers to support increasingly complex and powerful system architectures. Molded fan-out embedded bridge die interposers emerge as a highly scalable and cost-effective alternative to replace silicon interposer for processor-to-memory integration. 

However, traditional manufacturing techniques for embedded bridge die interposers encounter significant obstacles, including ultra-tight die placement tolerances (≤1 µm), overly large via capture pads that restrict routing density, and constrained bridge die aspect ratios that limit design flexibility. These challenges lead to increased production costs, scalability limitations, and yield problems—particularly in high-volume manufacturing.

This paper presents a novel design approach utilizing Adaptive Patterning® (AP), a design-adaptive method that transforms the traditional lithography process. By employing maskless laser direct imaging (LDI), AP creates a customized, optimized pattern for each device, dynamically aligning interconnect elements — such as dielectric vias and copper redistribution layers (RDLs) — to the precise die position of the embedded die within the molded interposer. This effectively offsets the die shift that occur during assembly, ensuring precise alignment, high yield, and reliable device performance.

This paper presents a test design showcasing the Adaptive Pad Stacks methodology, developed to address the key limitations of fan-out embedded bridge die interposers. By significantly increasing manufacturing tolerances, Adaptive Pad Stacks deliver a substantial improvement—by an order of magnitude—in both alignment precision and interconnect reliability. This enhancement enables scalable, high-yield production of complex interposers, which is critical for sustaining density scaling and ensuring consistent performance in high-volume, wafer and panel-based manufacturing.

Adaptive Pad Stacks offer a complementary and potentially more scalable approach by relaxing placement constraints through patterning flexibility. This not only reduces cost and complexity but also aligns well with emerging panel-level packaging trends, making it a promising alternative for next-generation heterogeneous integration.