SBLLocking: Localization of Optical Side-Channel Leakage in Logic-Locked Integrated Circuits through Structure-based Learning

Logic locking protects outsourced integrated circuit designs by obfuscating circuit functionality, thereby hindering reverse engineering, piracy, and overproduction. However, prior work has shown that logic locking is vulnerable to physical probing attacks such as Electro-optical Frequency Mapping (EOFM). In this work, we present SBLLocking, a structure-based learning framework that identifies potentially vulnerable circuit regions before fabrication. As a pre-silicon screening tool, SBLLocking helps designers identify candidate nodes for further validation and mitigation. It represents a gate-level netlist as a directed graph and uses structural and logic-derived features, including gate type, connectivity, logic level, and key-input dependence, to identify candidate EOFM-susceptible nodes. In this study, susceptibility is operationally defined using the SAT-based key-dependent distinguishability criterion introduced in CLAP. We evaluated SBLLocking on 500 unseen benchmark-derived and synthetically generated circuits. SBLLocking achieved 95.71% average node-level accuracy and a 1.72% false-negative rate in identifying CLAP-susceptible leaking nodes, with stronger performance on benchmark-derived circuits and only minor degradation on structurally diverse synthetic designs. SBLLocking required approximately \(2\times 10^{-3}\) s per circuit for inference and achieved a \(1.63\times 10^{8}\) runtime speedup over exhaustive node-level SAT analysis, demonstrating its practicality for scalable design-time EOFM susceptibility screening.