Reliability Evaluation for Realizing Panel-Level Packaging for AI/Data Centers and Vehicles

Recently, in power semiconductor applications such as AI/data centers and electric vehicles (EVs), there has been an increasing demand for reduced wiring resistance and inductance as power supply output currents increase.

　We are focusing on the development of power module packaging using chip embedded technology based on semi-additive metallization and coreless (without pre-preg) fan-out 300mm square panel-level processes.

　We have developed several chip-embedded packages such as GaN DC-DC half-bridge modules and SiC sub-module packages featuring ultra-thinness, low resistance, low inductance, and high heat dissipation, using direct copper plating on both sides of the chip and power chiplet technology to connect multiple chips in parallel. The very simple and scalable structure with no wire-bonding at the panel-level allows a large number of chips to be densely connected.

　For AI/data centers and vehicle applications, warpage during PCB, DBC and heat sink mounting, mechanical strength, and internal wiring reliability are critical. Understanding failure modes is also essential. 

　In this report, we evaluated the impact on the reliability of internal wiring connections by conducting not only normal environmental tests, such as temperature cycles, but also overload tests assuming attachment to DBCs and heat sinks.