Reducing Wafer-to-Wafer Bonding Misalignment to Enable 140nm Pitch Hybrid Bonding

A 140 nm pitch bonding test vehicle was created to evaluate <150 nm fine pitch wafer-to-wafer hybrid bonding. Void-free hybrid bonding with Cu grain growth across the bonding interface was demonstrated with <50 nm bonding residuals for a champion wafer. Bonding residuals were <40 nm for 99.5% of points tested with three standard fusion bonded wafers, highlighting the wafer bonder’s high precision and repeatability. Finally, a multi-physics bonding simulation of a new bonding hardware solution reduced bonding misalignment from 70 nm M+3σ to 14.6 nm M+3σ. 

As logic and memory scaling continues to slow, the demand for higher interconnect density and speed has increased in recent years, especially among NAND and DRAM companies. Device performance gains are increasingly being achieved in the back end of line using wafer-to-wafer (W2W) hybrid bonding for SRAM on Logic, 3D NAND, CIS, 3D-SoC, and eventually hybrid bonded CFET architectures. Hybrid bonding is a 3D integration technology to vertically stack heterogenous wafers with ultra-fine interconnect densities using direct Cu-Cu bonds formed at low temperature (200-400 °C). Traditional packaging technologies like microbumps are only able to scale down to 10 µm pitch, while hybrid bonding can form interconnects directly using Cu pads with 10 µm pitch down to <1 µm pitch, increasing the interconnect density, reducing RC delay, and shrinking package sizes. Previously, Tokyo Electron (TEL) demonstrated industry leading 1 µm and 0.5 µm pitch W2W hybrid bonding with 98% electrical yield across the entire wafer [1]. However, as AI and HPC applications continue to drive interconnect scaling, sub-150 nm pitch hybrid bonding will be needed to reach the required interconnect densities and performance targets.

To demonstrate sub-150nm pitch hybrid bonding, a 140nm pitch test vehicle was developed. The 140nm pitch test vehicle has asymmetric bond pads with smaller bond pads on the top wafer compared to the bottom wafer which increases the allowable misalignment before electrical yield is affected. A hexagonal bond pad layout was also used to increase the Cu density and spacing between adjacent pads. After initial integration, wafers were bonded with the newest generation TEL hybrid bonder and a high-accuracy bonding recipe was developed with residual misalignment <50nm. Bond misalignment analysis showed that the hexagonal bond pad layout was affecting the bond propagation, contributing to higher misalignment than pads with square packing. It was found that this propagation difference could be mitigated by switching the Si substrate crystal orientation from (100) to (110) due to the anisotropic mechanical properties of Si and the hexagonal packing of the (110) plane. From this development, 140nm pitch bonding was successfully implemented as demonstrated by Cu grain growth across the interface and void-free bonding. 

To further understand the contributors to wafer bonding misalignment, the high-accuracy bonding recipe was used on fusion bonded wafers to remove the impact of the bond pad layout. Among three wafers tested, the bonding residuals were <40nm for 99.5% of points tested indicating that the bond pad layout contributes to higher bonding residuals. Additionally, a novel bonding hardware solution to correct the bonding residuals was tested using a calibrated multi-physics wafer bonding simulation capable of predicting the bonding misalignment [2]. The novel bonding hardware solution reduced bonding misalignment from 70 nm M+3σ to 14.6 nm M+3σ according to the simulation results. These process improvements to reduce the residual misalignment enable continued pitch reduction for hybrid bonding and the next generation of 3D devices.