PWDD-Net: A Patterned Wafer Defect Detection Network for Semiconductor Manufacturing

Various wafer defects appear inevitably, due to the highly complex and precise semiconductor fabrication processes. Thus, precise and rapid detection of patterned wafer surface defects is essential to prevent circuit failures and ensure product quality. Accordingly, a novel lightweight detection network termed PWDD-Net is proposed in this work, by introducing several modifications on YOLO11-nano. First, a novel LGE block, incorporating spatial and channel transformation with adaptive gated mechanism, is developed to enhance fine-grained feature extraction and representation. Second, by integrating a self-calibration block, a lightweight SC-C3k2 module is proposed to improve global feature capture while preserving network efficiency. Finally, the Slide loss is employed to distinguish easy and hard instances, thereby mitigating the imbalanced class distribution and improving classification precision. Experimental results show that PWDD-Net achieves a mAP@0.5 of 74.4% and a mAP@0.5:0.95 of 46.5%, yielding remarkable increments of 4.2% and 2.1% over the YOLO11-nano baseline, respectively. In addition, the network maintains a comparable parameter scale to the baseline and performs an inference speed of 78 FPS using an NVIDIA RTX 3080Ti GPU. These results demonstrate the model’s potential for real-time industrial wafer defect inspection applications.