Process Integration of Direct Al-Cu Bonding Toward Heterogeneous Integration of 22nm CMOS FDSOI in Advanced RF Packaging

Advanced Packaging is pivotal to the growing demand for semiconductor industry that facilitates emerging applications such as Artificial Intelligence (AI), high performance computing, (HPC), autonomous vehicles, high end smartphones, 5G, Internet of Things and augmented reality. Recent advancements have ceased to adhere to Moore’s Law, which predicted that the number of transistors on a chip would double every 2 years. With this development, advanced radio frequency (RF) packaging has become a primary facilitator of system level performance than being a supporting technology.

In advanced CMOS nodes such as 22nm, aluminum (Al) is the standard top metallization layer in the back-end-of-line (BEOL) due to its strong adhesion to the dielectrics such as silicon nitride and silicon dioxide, thereby serving as a protection layer to prevent cracks and mismatches. Even though aluminum pads are widely acknowledged for wire bonding and flip-chip bump soldering, it is more challenging to bond bare die to copper (Cu) based silicon interposers. The challenge is the heterogeneous integration of dissimilar materials at the interface as the bonding chemistry is critical for successful electrical connection. Although under-bump metallization (UBM) is added as a barrier layer on the Al pads to prevent oxidation and improve the feasibility of bonding, it is worthwhile exploring the direct Al-Cu bonding to enable the flip-chip bonding of the bare die to the silicon interposer.

This research work focuses on the flip-chip bonding of 22nm CMOS FDSOI analog integrated circuit (IC) from Global Foundries (GF) with Al as the terminating layer and the silicon interposer designed with Cu as the top layer. Both aluminum and copper form oxides when exposed to air and these oxides impede the metal-to-metal bonding. Copper oxide growth is slow and can be controlled, whereas controlling the aluminum oxide growth is challenging and requires special measures such as inert environment or vacuum to keep the aluminum from oxidizing. Despite these challenges, we demonstrate that Al-Cu bonding is feasible in a controlled environment by employing surface activation, oxide removal and handling the samples in inertness until bonding. It is of significant benefit to bond directly to aluminum pads on the chip as it removes the need for post processing fabrication step such as UBM, resulting in reduced time and cost.  

In this work, we present bonding workflow in two stages – (1) bonding of test vehicles and (2) bonding of a 22nm CMOS FDSOI analog chip from GF to the designed silicon interposer. In the first test vehicle, 50Ω Coplanar Waveguide (CPW)-to-CPW configuration is implemented, where the CPW on test chip is bonded to the CPW on the interposer. This stage is critical as it provides the platform to evaluate the impedance, scattering parameters, alignment tolerance, surface roughness and the bonding parameters that can be applied to the 22nm die bonding. In the second test vehicle, 50Ω coplanar strip lines (CPS)-to-CPW configuration is realized, where the CPS on test chip is bonded to the CPW on silicon interposer. This test vehicle ensures that the transition from CPS to CPW can be verified and the differential-to-single-ended impedance conversion is evaluated. Both the test vehicles employ Cu as the top metallization layer on the silicon interposer and Al on the test chip. The interposers and test chips are fabricated on high resistivity silicon substrates with silicon nitride (SiN) as the dielectric layer. Following the test vehicle verification, the bonding parameters are applied to bond the 22nm analog die to the specifically designed silicon interposer enabling on-wafer characterization of the bonded die.  

The silicon interposers and the test chip were fabricated at the Aggiefab Nanofabrication facility at the Texas A&M University while the thermocompression bonding was performed at the Nanofabrication facility at the Rice University using the Finetech Fineplacer Lambda die bonder. Electrical measurements are done using the FormFactor EPS150MMW probe station at the Intelligent Electromagnetic Sensor Laboratories (iEMSL) at Texas A&M University. Measurement results such as S-parameters, SEM of the cross section of the bonded interface will be presented in the extended abstract.

            In conclusion, this research focuses on the bottleneck in advanced packaging on the heterogeneous integration of dissimilar materials Al-Cu and a novel approach to bonding and package design. The bonding workflow explained here establishes a valid pathway for the direct bonding of the BEOL 22nm CMOS dies, advancing RF packaging concepts applicable to 2.5D and 3D integration architectures and interconnect novelty, which are in direct alignment with the IMAPS themes.