Preparation of Facet-Free 8-Inch n-Type 4H-SiC Substrates

Abstract

During the growth of n-type 4H-SiC crystals by the PVT method, the resistivity in the facet region is lower than that in the non-facet region, which reduces cutting efficiency during laser slicing as the facet area requires repeated cutting. In addition, the facet region is prone to the multiplication of TEDs and stacking faults, resulting in a higher defect density that degrades the substrate quality. Therefore, the preparation of facet-free substrates is particularly important for improving the efficiency of laser cutting and the quality of the substrate. In this study, the growth was carried out on the 4° off-axis 4H-SiC seed with a diameter of 220 mm. A specific thermal field was constructed through theoretical analysis and thermal field simulation for crystal growth. In this thermal field, the facet was located at the edge of the crystal and had a small width. Subsequently, the facet was removed by off-center cropping during the rounding stage. Finally, facet-free 8-inch n-type 4H-SiC substrates were obtained through slicing, grinding, and polishing. Substrate scan images, resistivity distribution maps, and Raman mapping images of the LOPC mode confirmed that the obtained substrates were facet-free. The facet-free substrate exhibits a low TED density and is free of stacking faults, and its resistivity heterogeneity is only 0.9%, significantly lower than that of substrates with facets. Moreover, the in-plane free carrier concentration difference of the facet-free substrate was minimal, indicating high electrical property uniformity.