Practical RIS Design: Scalability, Tolerance, and Calibration

Reconfigurable intelligent surfaces (RISs) require joint choices of tuning element, addressing, tolerance, and calibration. This paper presents a conditional co-design framework evaluated analytically and through reproducible numerical experiments. A perimeter-capacity ratio screens specified edge-escape architectures while distinguishing external wiring from independent per-cell control. Its illustrative one-square-meter boundary depends on line multiplicity, routing pitch, and usable layers and does not prove PCB unroutability. A coupled tolerance study compares ensemble variance, realization RMS, and piston/tilt-removed RMS. Spatial structure changes sidelobes and pointing, while apparent peak-gain recovery with correlation partly depends on normalization. Scan-specific checks correct a phase-datum sensitivity in two-bit quantization. A balanced four-phase power protocol separates complex state contrasts from an anchored physical cell lookup table. Decision-margin tests replace a universal coupling threshold; joint noise and multipath experiments state the reference, rank, and stationarity conditions. Short delay-line cells are distinguished from full-aperture true-time-delay control. A revised 28 GHz architecture comparison includes serial per-cell storage, uncertainty intervals, and requirement sensitivity. Multiple candidates satisfy the pattern, latency, and perimeter screens under stated command laws; physical stack-up, non-linear tuning, and stationarity still require hardware-specific verification. The framework supports traceable design comparisons rather than universal frequency, resolution, or manufacturing limits.