Practical Considerations in 7 nm and 16 nm FinFET LNA Design: A Comparative Study

This paper presents the design and experimental characterization of two low-noise amplifiers (LNAs) operating at 5 GHz, implemented in commercial 16 nm and 7 nm FinFET CMOS technologies. Both circuits employ a cascode common-source architecture, but adopt different design approaches. The 7 nm implementation was designed to achieve simultaneous noise and input matching through source degeneration and gate inductive tuning. In contrast, the 16 nm implementation was primarily optimized for the minimum noise figure using an iterative electromagnetic-aware design methodology. The measured results highlight the practical trade-off between theoretical simultaneous noise and impedance matching and the degradation introduced by large integrated passive components in deeply scaled FinFET technologies. While the 7 nm design achieved improved input and output matching around the target frequency, the required inductive network introduced additional passive losses that degraded the measured noise figure. Conversely, the 16 nm implementation achieved a lower measured noise figure through a simplified matching network, at the expense of a reduced input-matching performance. The comparison provides practical design insights into the implementation of RF front-end circuits in advanced FinFET technologies and highlights the impact of passive component losses on the achievable noise performance.