Power‐Off Data Preservation and Recovery Circuit Based on Ferroelectric Field‐Effect Transistors

ABSTRACT

To address the issue of data loss caused by unexpected power outages, a power‐off data preservation and recovery circuit based on N‐type ferroelectric field‐effect transistors (FeFET) is proposed. The circuit consists of a write control module, a data recovery module, transmission gates, and FeFETs. By binding the write operation to the supply voltage drop event, a single write is performed only at the moment of power failure, avoiding endurance degradation caused by frequent FeFET writes. The circuit supports four modes: initialisation, normal operation, power‐off retention and power‐on recovery. Cadence simulation results verify that the circuit can accurately latch the logic state of data during power failure and is compatible with standard CMOS processes. This design provides a highly reliable and low‐power power‐off data protection scheme for applications such as energy management and aerospace equipment.