Power Switch Network Optimization Using Machine Learning for Inrush Current and Wakeup Latency Prediction

Today’s large-scale designs leverage power gating to achieve low power consumption, which necessitates the design of an efficient power switch network that accounts for both inrush current and wakeup latency. Optimizing this power switch network involves striking a balance between minimizing inrush current and reducing wakeup latency. However, analyzing inrush and wakeup latency for a given network is computationally expensive, particularly for complex systems, making optimization frameworks that rely on analysis engines prohibitively slow. To address this challenge, we frame the analysis of inrush and wakeup latency as a regression problem and train machine-learning (ML) models to predict these metrics. The ML model achieves mean errors of less than 10% for inrush current prediction and for wakeup latency prediction, while providing a speedup of over 50× compared to SPICE. By leveraging an ML model, we efficiently explore the design space and identify optimized power switch network patterns that minimize both wakeup latency and inrush current.