Power Delivery in Advanced IC Packaging

As AI workloads continue to push the boundaries of semiconductor performance, power delivery has become one of the most critical challenges in advanced package design. Chiplet-based architectures are driving dramatic increases in transistor counts, power density, and system complexity, placing new demands on package construction and power distribution networks. In this presentation, we will examine how advanced packaging technologies are evolving to support next-generation AI and high-performance computing applications. Attendees will gain insight into emerging package fabrication methods, advanced design and test approaches, decoupling capacitor strategies, and techniques for minimizing parasitic inductance in increasingly complex package environments.

The session will also explore how new 2D and 3D integration approaches, high-density module manufacturing, and advanced packaging infrastructure are enabling the performance, scalability, and reliability required for tomorrow’s AI-driven systems.