Performance-limiting electron and hole traps in 4H-SiC PiN power diodes determined by combined DLTFS and TCAD studies

The performance-limiting electron and hole trapping centers in 4H-SiC PiN power diodes are determined by combined deep-level transient Fourier spectroscopy (DLTFS) experiments and technology computer-aided design (TCAD) simulations. Two electron traps E1 (EC − 0.19 eV) and E2 (EC − 0.67 eV) and three hole traps H1 (EV + 0.16 eV), H2 (EV + 0.3 eV), and H3 (EV + 0.63 eV) are detected by DLTFS. Since DLTFS measurements were limited to 400 K, a few deep-level defects could not be detected in our experiments. In addition to the traps identified by DLTFS, two deep levels commonly reported at elevated temperatures, E3 (EC – 1.65 eV) and H4 (EV + 1.43 eV), are integrated into the TCAD model to perform a reliable trapping analysis. The effects of electron traps, hole traps, and individual traps are evaluated by selectively excluding them from the simulation. Hole trapping is found to be more prominent than electron trapping in pristine (as-fabricated/untouched) diodes. Among the traps, shallow hole trap H1 exhibits a strong impact in reducing the conduction current (followed by E3) in pristine diodes. To explore the fundamental nature of each trap, the concentration (NT) of an individual trap is increased to a higher value without changing the NT of other defects. Subsequently, the diode characteristics are analyzed at higher NT of the specific trap. The traps E2 and E3 significantly reduce the diode current at higher NT. The deep acceptor E2 is primarily responsible for the donor doping compensation in the n− drift layer.