Parallel Algorithms for Power and Signal Integrity Analysis of High-Speed Designs

Modern VLSI designs are posing ever increasing challenges for computer-aided design tools. This paper provides an overview of recent developments in parallel algorithms for signal and power integrity analysis in high-speed designs. Efficient partitioning and simulation algorithms have been developed employing

waveform relaxation iterations for application to signal and power integrity analysis. Unlike direct solvers, the described algorithms are highly parallelizable and yield significant speed-ups. Numerical examples are presented to demonstrate the validity and efficiency of the presented methods.