Opposite Trap‐State Evolution Pathways Govern Endurance and Retention Failure in Amorphous Chalcogenide Memory
Byung Jun Lee, Won Hee Jeong, Min Kyu Yang, Gun Hwan KimABSTRACT
Selector‐only memory (SOM) is a promising next‐generation memory architecture that integrates both selector and memory functionalities within a single two‐terminal chalcogenide device. Despite its structural simplicity, the reliability of SOM devices remains poorly understood at the mechanistic level. Here, the failure mechanisms governing endurance, retention, and threshold voltage (V th ) drift of GeSbSe SOM devices are systematically investigated through physical and electrical analyses. Under endurance cycling, time‐of‐flight secondary ion mass spectrometry (ToF‐SIMS) reveals a preferential reduction of Se content, reorganizing the trap environment toward shallower states, confirmed by Poole–Frenkel (P–F), Arrhenius, and drive‐level capacitance profiling (DLCP) analyses. Trap shallowing drives a gradual decrease of both V th states, while heteropolar bond depletion weakens the polarity‐dependent trap response asymmetry, narrowing the memory margin and leading to endurance failure. Under retention and V th drift, x‐ray photoelectron spectroscopy (XPS) and Raman spectroscopy reveal that thermal stimulation drives short‐range structural relaxation toward deeper trap states, directly driving time‐dependent V th rise and asymmetric V th drift. Furthermore, cycling‐induced depletion of Se‐related bonding resources amplifies susceptibility to structural relaxation, establishing a self‐reinforcing degradation pathway that accelerates memory margin loss. These findings establish a unified trap‐based framework linking atomic‐scale structural changes to device‐level reliability degradation.