On-Shore Manufacturing of Fan Out Wafer Level Packaging (FOWLP) at 300mm Wafer Size with Fine Redistribution Layers for High-Bandwidth Interconnects

On-shore manufacturing of semiconductors has become increasingly important to the national security of the United States and supply chain resilience of a variety of industries mitigating the risks in the presence of geopolitical conflicts, natural disasters and the pandemic. In spite of recently announced public and private investments into on-shore semiconductor manufacturing including the CHIPS and Science Act, advanced packaging of semiconductor chips remain undersupplied in US, falling behind the surging demand by artificial intelligence, medical devices, defense and aerospace. In particular, a large-scale and low-cost 2.5D solution is needed to be established in a domestic manufacturing facility to address the growing demand of heterogeneous integration. 

Funded by DoD’s RESHAPE program, SkyWater Technology has spearheaded an effort to reshore FOWLP packaging technologies at its manufacturing facility in Florida, the first FOWLP line in the US with a full manufacturing-grade equipment set and advanced lithography capabilities. Licensed from Deca Technologies, this technology allows large-scale integration of multiple incoming semiconductor chips over the entire 300mm wafer area without reticle limit. This flexibility of an unlimited FO package size is enabled by Laser Direct Imaging photolithography capable of defining line / spaces down to 2 um, combined with adaptive patterning developed by Deca to dynamically adjust the RDL patterns to accommodate die shift after die placement during the manufacturing process. Being able to provide down to 20um I/O pitch on the integrated chips and up to 5 RDL layers on both sides of the molded body, this technology offers high-bandwidth interconnect with design flexibility for a 2.5D package. The Cu Post Via (CPV) through the mold layer connecting RDL on both sides enables vertical power delivery and signal connections for minimized IR drop and improved power / signal integrity. CPV also allows multiple 2.5D package to form a 3D stack for high-density integration. For applications not requiring very large package size with many integrated die, this FO package can be directly mounted onto PCB in absence of a substrate, leading to improved performance of the overall system with lower latency and power consumption, as well as cost reduction.   The results of the initial stages in this FOWLP test vehicle design and development at 300mm wafer size will be presented in this paper, with a set of daisy chains designed across the via / RDL / UBM.  SkyWater is executing a plan for a first article showing FOWLP process development and qualification for production, with advantages in scalability, design flexibility, cost, customization and time to market.