Near Chip Scale Package for High Power, Big Chip LEDs

High power LEDs are rapidly evolving into devices that progressively bear less and less resemblance to the LEDs that we used to know. Today’s LEDs feature higher brightness levels, higher operating power levels, larger die/emitter sizes, a shift from edge emission to surface emission, enhanced extraction and collimation of light, and increased efficacies. These changes are enabling applications that until now have been dominated by mercuryarc, high intensity discharge, halogen, incandescent and fluorescent bulbs, and previously were beyond the capability of LEDs. Now that LEDs can compete in many high brightness applications previously occupied by more traditional forms of lighting, new innovative forms of LED packaging are required. Handling high-density thermal dissipation, high optical power levels, tight mechanical tolerances and high current electrical interconnects now require packaging approaches that were previously unconventional, even unheard of, for LEDs. In order to address these new LED package requirements, a near-chip-scale package has been developed which is a drastic departure from traditional LED packages. This new packaging platform has borrowed from, and built on, a mix of packaging technologies more commonly associated with laminate array style BGA, CSP, and flip-chip devices. This paper presents the challenges encountered, and solutions implemented during design of the package and the associated process development. The package structural, thermal, optical and electrical design inputs are presented as well as the subsequent design approaches, including materials selection, risk prioritization, and designing for manufacturability and reliability. The resultant package is a revolutionary, very compact, surface mount device which features a junction-to-case thermal resistance of <0.6 degrees C/W for a 12 mm2 LED die, zero optical loss (100% transmission), close proximity optical interfacing due to elimination of wirebonds and their associated loop heights, excellent compatibility with state-of-the-art assembly manufacturing lines, and design flexibility including potential for MCM and SiP integration.