Nanoscale Characterization of Cobalt Exposure in Nano-through-Silicon Vias via Photoinduced Force Microscopy: Implications for 3D Interconnect Architectures

Abstract

As semiconductor manufacturing advances toward three-dimensional (3D) integration architectures, the precise chemical mechanical polishing (CMP) of high-aspect-ratio (HAR) nanothrough-silicon vias (n-TSVs) utilizing cobalt (Co) interconnects has become critically important. However, achieving nanoscale, nondestructive, and accurate evaluation of Co core exposure and interfacial planarization during the CMP process remains a formidable metrological challenge. Herein, we report the reliable nanoscale compositional characterization of SiO2/TiN/Co n-TSV heterostructures across progressive CMP stages using a custom-built 405 nm photoinduced force microscopy (PiFM) system capable of simultaneously acquiring optical force amplitude and phase signals. By leveraging both amplitude and phase mapping, together with material-dependent variations in the relative contributions of repulsive photothermal expansion forces and attractive optical gradient forces, PiFM precisely tracks the nanoscale structural evolution of n-TSVs during CMP–specifically, the progressive removal of overlayers and the eventual unmasking of the Co core. Notably, we demonstrate that the optical force phase signal provides clearer material contrast and improved detection sensitivity compared to conventional optical force amplitude imaging. This phase-sensitive contrast enables reliable differentiation of complex heterogeneous interfaces and tracks localized Co core exposure, as well as subsequent material depletion due to overpolishing. Finally, correlative conductive atomic force microscopy validates the polishing progression and Co exposure logic inferred by PiFM. This work establishes 405 nm PiFM as a promising, facile, and nondestructive metrology tool. By leveraging both optical force amplitude and phase signals, it provides critical feedback for characterizing nanoscale material interfaces and evaluating polishing quality in Co-based n-TSV interconnects, thereby facilitating CMP process optimization and improving the reliability of next-generation 3D interconnect architectures.