Nanoporous Silicon Capacitors for Advanced Power Delivery Networks (PDN)

Recent advances in Nanoporous Silicon Capacitor (NPC) technology are addressing the stringent requirements of modern Power Delivery Networks (PDNs) in both mobile devices and high‑performance computing (HPC) systems. Developed using dedicated in‑house manufacturing capabilities and in collaboration with European research laboratories, this innovation delivers exceptionally high capacitance density—currently up to 4 µF/mm² with a future roadmap targeting 8 µF/mm²—combined with low ESL/ESR and stable performance over wide temperature ranges.

In this presentation, we will describe the structure and operating principles of the NPC technology, highlight reliability data exceeding 10 years, and demonstrate compatibility with advanced packaging solutions. We will show how multi-terminal and array-based NPC configurations enable flexible design customisation, supporting tailored pad layouts, assembly options, and electrical characteristics to match specific requirements.

Measured and simulated results reveal substantial reductions in PDN impedance—up to 92% with multi-terminal arrays—leading to reduced voltage ripple and rapid voltage stabilisation, directly benefiting both mobile and HPC applications. Finally, the roadmap will be discussed, including development directions such as hybrid bonding and direct stacking of NPC dies beneath processors, paving the way for Generation 4 NPCs aimed at further integration and performance gains.

This work demonstrates how NPC technology can meet the evolving demands of next‑generation PDNs, offering system designers a fully customisable and high‑performance passive solution for challenging power delivery applications.