Multi-die Wirebond Development of S32E Automotive Real-Time Processor

NXP’s unified architecture of automotive processors, the S32 platform, is designed to meet the increasing demands of vehicle architectures from the vehicle computer to the domain and zonal controllers, while also addressing safety processing. The S32Z2/E2 real-time processors family share deterministic multicore Arm Cortex-R52 compute with split-lock support, dual-core lockstep Cortex-M33 processor cores, a DSP/ML processor, along with communications acceleration, and support ISO/SAE 21434 cybersecurity and ISO 26262 ASIL D functional safety. In particular, the E2 series is designed with additional capabilities including 5V analog and I/Os with complex times, targeted primarily towards electric vehicle (xEV) control and smart actuation. 

The S32E2 represents NXP’s first 27x27mm wire bond MAPBGA System-in-Package (SiP) solution that successfully integrates three distinct silicon dies into a single compact device. This innovative configuration includes a 16nm Fin FET Compact (FFc) CPU die, an analog die embedded with non-volatile memory, and a separate Flash memory die. This paper highlights the design and assembly innovations that enable this multi-die integration. The package family is designed with flexibility, offering multiple Flash memory die size options, as well as a variant without the Flash die—all supported by a common substrate layout.

Built on a chiplet-style architecture, the interconnection between the CPU and analog die is achieved through direct die-to-die wire bonding, while the CPU-to-Flash communication is routed via the substrate. The substrate itself is optimized using a bussless configuration, which enhances routing density and channel availability. Additionally, the circuit layout ensures that all bond wires are kept under 3mm in length, effectively minimizing resistance, inductance, and capacitance (RLC) losses—an impressive feat for a 4-layer laminate substrate.

Both gold and copper wire materials are employed to support the three-die configuration. The assembly process utilizes a three-pass die attach flow, which ensures precise die placement and alignment. One of the major challenges in the assembly process was developing a reliable copper wire bonding technique on a 28kA thick aluminum metal layer with a 10-metal-layer (10ML) back-end-of-line (BEOL) stack, including a single Mu layer. To address this, several wire bonding recipes were explored using hybrid and gentle bonding parameters. These were rigorously tested for reliability, and an optimized hybrid bonding recipe was selected based on its superior pad crack resistance after temperature cycling. This recipe also minimizes the ball bond-to-pad contact area, enhancing mechanical integrity.

The final device has successfully passed AEC Grade 1 qualification, demonstrating excellent assembly robustness and high final test yields. The implementation of this complex, 1GHz-capable device using wire bond BGA technology has resulted in a significantly lower packaging cost compared to a flip-chip alternative, making it a cost-effective and technically sound solution for high-performance applications.