Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing

ABSTRACT

In‐memory computing using memristor crossbar arrays promises to overcome the von Neumann bottleneck, yet interface‐type memristors suffer from inherent current–voltage nonlinearity that degrades analog accuracy. Here we introduce a memristive‐gated RC‐delay synaptic transistor that encodes analog inputs in the time domain via a single RC mechanism, structurally bypassing this nonlinearity. A self‐rectifying Al: TiO ₂ memristor at the transistor gate controls the RC time constant, yielding eight (3‐bit) nonvolatile analog states; independently of the state count, the charge readout at each fixed state is quasi‐linear with respect to the input voltage (R ² > 0.985). Asymmetric charging/discharging dynamics enable single‐ and three‐pulse time‐domain encoding of 8‐level inputs. The same integrated device architecture further provides volatile STP‐like transient dynamics—an RC fading‐memory kernel sampled within the read frame—for reservoir‐state generation, together with nonvolatile multilevel states serving as long‐term‐plasticity (LTP) readout weights. Using experimentally measured device characteristics, hardware‐calibrated simulations demonstrate 95.92% classification accuracy on MNIST handwritten digit recognition and accurate Mackey–Glass chaotic time‐series prediction (NRMSE = 0.029, R ² = 0.987). This architecture provides a practical route toward DAC/ADC‐minimized analog in‐memory computing.