Low Power Reconfigurable Neuromorphic Architecture by Sparsely Connected Spiking Neural Networks for Edge Applications

Recent advances in biologically inspired neural computation have sparked increasing interest in developing hardware-efficient architectures capable of emulating brain-like cognitive abilities like low power consumption and less inference latency. However, significant hardware overhead and spike-processing complexity remain major challenges in FPGA implementations of spiking neural networks. In this work, we propose a sparse spike-aware and weight pruning FPGA architecture based on LIF neurons that minimizes spike activity and synaptic operations through pruning-aware event-driven computation. The proposed sparse spike-aware SNN architecture was evaluated using the Iris dataset. The dataset was divided into 80% training and 20% testing samples. Pre-trained weights obtained from software-level training were deployed onto the FPGA-based LIF classifier. Classification accuracy was computed by comparing predicted output spikes against ground-truth class labels. Experimental results demonstrated that the proposed architecture achieved an overall classification accuracy of 93.3% while maintaining low hardware resource utilization and reduced power consumption. Moreover, the implementation achieves superior energy efficiency, consuming only 3.5 W total on-chip power and utilizing 587 logic cells, confirming its suitability for compact, real-time edge computing neuromorphic applications.