Low-Energy Organic Ferroelectric Synaptic Transistors Enabled by Interfacially Engineered Gate Insulators

Abstract

Solution-processed organic ferroelectric transistors are promising synaptic components for portable and wearable neuromorphic systems. However, compared with oxide-based platforms, these transistors generally require relatively thick ferroelectric gate layers and, consequently, high operating voltages because of the difficulties of achieving a well-developed crystalline phase and high electrical insulation during solution processing. This requirement hinders the practical implementation of organic ferroelectric transistors in energy-efficient neuromorphic hardware. Here, we report an energy-efficient organic ferroelectric transistor architecture based on a gate insulator comprising a thin crystalline ferroelectric film and an ultrathin oxide blocking layer. The crystalline ferroelectric film enables stable polarization switching, and the oxide blocking layer suppresses gate leakage, allowing reliable synaptic operation at low voltage and current levels. Owing to these energy-efficient synaptic characteristics, hardware neural networks constructed from the developed memory devices classify clothing images with high accuracy while consuming only ∼0.82 pJ per recognition event, approaching the energy scale of biological systems. This strategy provides a practical route toward energy-efficient neuromorphic applications in portable and flexible electronics.