Large Signal Linearity Analysis for TIA and Bias Optimization with a Power Series

This work mathematically analyzed the large signal linearity of Trans-Impedance Amplifier(TIA) with a power series as a transfer function for the circuit. A conventional TIA circuit is presented with CMOS 65-nm process devices, and the large signal linearity is improved by a couple of methods for a load-line theory and a bias optimization. Comparing with P1dB for the proposed circuit simulation, the analysis is validated for optimizing the large signal linearity. This work achieves 7.83 dBm OP1dB under 50 MHz BW with 2.5 V supply voltage.