Interfacial Layer Engineering for Memory and Reliability Enhancement in Hf0.5Zr0.5O2 FeFETs

The interfacial layer (IL) in the gate stack of Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs) strongly affects device performance and reliability. In this work, high-κ IL engineering is investigated using calibrated TCAD simulations and experimental verification to study the role of dielectric constant, physical thickness, and interface traps on the performance enhancement of HZO FeFETs. Typical higher-κ materials, namely, Si3N4, Al2O3, and HfO2, are chosen as ILs. At a fixed physical IL thickness of 2 nm, increasing κ reduces the voltage drop across the IL and redistributes a larger fraction of the applied voltage to the HZO layer, thereby promoting more complete polarization switching. The simulated memory window (MW) consequently increases from 0.77 V for SiO2 to 2.20 V for HfO2. In contrast, at a fixed EOT of 1 nm, the memory performance of the FeFETs remains nearly unchanged among different IL materials, while higher-κ ILs substantially reduce the electric-field stress across the IL, suggesting a potential benefit for gate-stack reliability. Experimental measurements of the no-IL, SiO2-IL, and HfO2-IL devices are further used for model calibration and interface-trap analysis. By incorporating IL-associated interface traps into the calibrated model, the experimentally observed MW differences are discussed in terms of both interface-related effects and IL dielectric properties. These results clarify the condition-dependent benefits of high-κ IL engineering and provide design guidance for improving the memory performance and electric-field management of scaled HZO FeFETs.