Interface Effects in Ultrathin Silicon on Insulator Films
Andrea Pulici, Gabriele Seguini, Fabiana Taglietti, Roman Gumeniuk, Riccardo Chiarcos, Michele Laus, Johannes Heitmann, Marco Fanciulli, Michele PeregoABSTRACT
Dopant ionization in ultrathin Si films remains poorly investigated at the nanoscale. In this work, independent control of device layer thickness ( H SOI ) from 30 to 8 nm, dopant concentration ( n D ) from 10 18 to ∼10 20 cm −3 , and interface quality establishes a systematic framework to discriminate how bulk and interface phenomena affect charge transport in P‐doped silicon‐on‐insulator (SOI) films. When H SOI = 30 nm, transport properties are fully compatible with similarly doped bulk Si. Conversely, when H SOI < 30 nm, a concomitant carrier dose ( N e ) and mobility ( µ e ) reduction is observed. This effect, enhanced decreasing n D , is attributed to non‐passivated interface states at the Si/SiO 2 interface and can be significantly mitigated by rapid thermal oxidation (RTO). Electron‐paramagnetic resonance (EPR) and capacitance‐voltage (CV) measurements allow the correlation between the quality of the RTO‐SiO 2 /Si interface and electrical properties. After interface engineering, low‐temperature electrical characterization revealed a shift of the critical dopant concentration corresponding to the metal‐insulator transition and a significant increase in P ionization energy ( E d ) in samples with H SOI ≤ 15 nm. These results are discussed considering the dielectric mismatch between Si and SiO 2 and the electrostatic confinement within an ultrathin conductive channel, which arises from Si device layer depletion induced by electron trapping at the Si/SiO 2 interface.