Implementation Tradeoffs for Polar Codes in Communications Systems

Polar codes are a leading candidate for forward error correction (FEC) in short-block, burst-mode communication systems, yet few researchers have examined how they should be implemented in practice, including where the codec should sit on a mixed FPGA–processor platform. This paper evaluates that choice under direct-sequence spread spectrum (DSSS) ultra-reliable low-latency communication (URLLC) constraints on a system-on-chip with limited FPGA fabric area (Xilinx ZCU106), comparing six implementations across three locations: inline in the FPGA fabric, as a co-processor in the FPGA fabric but controlled by the ARM, and entirely in the Cortex-A53 software. The FPGA codec is area-bounded, which is reflective of the embedded space: a single datapath covering every code size in the waveform, which is selectable at runtime. The software is entirely off the shelf, including generated unrolled decoders. Each implementation is measured on end-to-end latency, throughput, energy per information bit, marginal hardware cost, and implementation flexibility. Software beats the co-processor, which was the only FPGA configuration built in hardware, on every metric, and the modeled inline placement only leads in latency for block lengths at or below N=64. The concluding design tradeoff is not a question of whether FPGA can decode faster than a processor, since with enough area it plainly can, but rather whether the area it can afford to spend is enough to justify placing the codec there.