Impact of Metal Fill on On-Chip Interconnect Performance

In Chemical Mechanical Polishing (CMP) employed in advanced IC fabrication processes, dummy metal fill structures are added in the low metal density areas to achieve global uniformity. It is important to study the impact of metal fills on on-chip transmission line structures as these topologies are gaining more importance for longer interconnections in high speed, low power VLSI designs. The addition of floating or grounded metal fills leads to capacitive and inductive parasitic loading of interconnects. This in turn results in impedance mismatches, increased delay, dispersion and increased loss. This paper deals with the analysis of on-chip interconnects considering metal fills. The first contribution of this work is to show the effects of metal fills on transmission line characteristics. We show the change in frequency dependent behavior of characteristic impedance and propagation constant when metal fills are inserted. We further study the impact of metal fill placement, feature size and shape on the transmission line characteristics. We show that for a »50% metal density, 9μmx9μm metal fill increases the distributed capacitance by »30% and distributed resistance by »29%. In comparison, smaller metal fills of 3μmx3μm result in a distributed capacitance increase of »20% and distributed line resistance increase of »19% for the same metal density. Octagonal metal fill for the same metal fill area (81μm2) improves the performance by reducing the capacitive impact to »26% and loss impact to »16%. This work concludes with design recommendations for on-chip transmission lines considering metal fills.