Homoepitaxial GaN-on-GaN trench MOSFETs with 438 MW/cm2 figure of merit and improved gate reliability

In this paper, we report enhanced high-voltage blocking capability and improved gate dielectric reliability in vertical GaN-on-GaN trench metal–oxide–semiconductor field-effect transistors (MOSFETs) through fabrication process optimization. A thick bottom dielectric (TBD) is introduced at the trench bottom to suppress the peak electric fields in both the gate dielectric and the GaN layer, resulting in a substantial improvement in breakdown voltage (VBR). The fabricated fully vertical device exhibits a low specific on-resistance (RON,sp) of 1.46 mΩ cm2, a maximum drain current density (ID,max) of 2.5 kA/cm2, an on/off current ratio (ION/IOFF) of 1010, and a VBR of 800 V, thereby achieving a competitive Baliga's figure of merit of 438 MW/cm2. In addition, due to the increased gate-drain distance, the output capacitance (COSS) of the device is reduced by more than 14%, which is beneficial for reducing the switching loss. Reliability measurements, including positive bias threshold voltage instability and step-stress gate breakdown tests, indicate that the TBD improves the voltage tolerance of the gate dielectric without introducing additional instability at the channel interface. Interface trap density (Dit) at the trench sidewall is characterized by the conductance method, which is found to be 1 × 1012 cm−2 eV−1. Furthermore, trap-assisted tunneling analysis of the gate leakage extracts a trap level of ∼1.3 eV within the Al2O3 gate dielectric, which accounts for the wear-out behavior under step-stress breakdown. This work demonstrates the effectiveness of the TBD technique for the development of high-performance and reliable GaN trench MOSFETs.