Hardware-Aware Co-Design of a Lightweight FPGA Accelerator for Palm-Vein Recognition

Palm-vein recognition is an attractive biometric modality for secure access control because its subcutaneous vascular patterns are difficult to observe and reproduce externally. However, existing studies optimize the recognition algorithm and the hardware accelerator in isolation, and rarely satisfy the on-chip memory and energy constraints of edge devices. This paper presents a hardware-aware co-design of a lightweight FPGA accelerator for palm-vein recognition, in which the network is shaped by the cost structure of the target fabric and the inference engine is organized around the resulting layer shapes. On the algorithm side, a hardware-aware neural architecture search with deployment cost terms is combined with divisor-aligned structured pruning and INT8 quantization-aware training. Structured pruning reduces the model parameters to 0.32 M and the MACs to 87.2 M while preserving recognition accuracy. On the hardware side, a task-specific design space exploration selects a 14×12 systolic array and an output-stationary dataflow that keeps all feature maps and weights on chip and reduces the modeled buffer-access count by 34.6% relative to the best alternative stationary dataflow. Implemented on a Xilinx Zynq-7100 at 100 MHz, the deployed INT8 checkpoint attains an accuracy of 99.50%, with a PL inference latency of 33.03 ms and an energy efficiency of 33.27 FPS/W.