Hardware-Assisted Dynamic Quantization for Low-Power DNN Inference on Edge FPGAs

Energy efficiency poses a significant challenge when deploying Deep Neural Networks (DNNs) on resource-constrained Edge AI hardware. Traditional quantization strategies often rely on a fixed bit-width during execution, creating a rigid trade-off between energy consumption, latency, and network accuracy. To tackle this issue, we introduce a hardware-assisted dynamic quantization control framework leveraging a Hardware/Software Co-Design approach, capable of dynamic precision scaling across a wide spectrum from 16-bit down to 2-bit. By implementing a lightweight ingress FIFO buffer at the FPGA hardware level, the system observes input stream congestion in real time and autonomously orchestrates precision-control signals on the fly, mitigating simulated buffer backlog and suppressing frame drops during burst traffic scenarios. A hysteresis-damped hardware finite state machine (FSM) controller is integrated to ensure operational stability without host-CPU intervention. Experimental evaluation via PyTorch-based co-simulation alongside physical hardware synthesis on an AMD Xilinx Zynq-7000 FPGA (Digilent ZedBoard) using the German Traffic Sign Recognition Benchmark (GTSRB) demonstrates that the proposed framework achieves 94.35% ± 0.05% Top-1 accuracy across five independent evaluation runs, matching the 16-bit baseline within 0.02 pp, while dynamically relieving queue pressure. Furthermore, the dedicated control-plane logic incurs a low resource footprint utilizing less than 0.01% of FPGA logic resources (three LUTs and one Flip-Flop) and a standalone dynamic power of 7.0 mW (projected to <1.0 mW for core logic in integrated SoCs), providing an autonomous, low-overhead supervisory control mechanism for adaptive edge inference.