Hardware Aspects of Machine Learning-Based Cardiac Fibrillation Diagnosis

This paper presents the hardware aspects of a Hjorth-parameter deep neural network (DNN)-based cardiac fibrillation diagnosis pipeline targeting low-power Internet of Medical Things (IoMT) devices and ASIC implementations. Building on earlier edge-to-cloud studies where Hjorth activity, mobility, and complexity were computed in software on microcontrollers and classified by a floating-point DNN, we introduce a fully synthesizable fixed-point hardware module that computes these parameters in real time, together with a quantized neural network (QNN) operating directly on the resulting fixed-point features. The Hjorth block includes derivative generation, accumulator banks, variance computation, and hardware divider and square-root units. Using the Shandong Provincial Hospital Database (SPHD) as in our previous work, we evaluate the impact of end-to-end fixed-point quantization on the AF-related arrhythmia detection performance for bit widths between 6 and 16 bits. For 10–12-bit configurations, the quantized pipeline achieves accuracy of approximately 93.7% and an area under the ROC curve (AUC) above 0.97, closely matching the floating-point baseline while significantly reducing the arithmetic complexity and memory footprint. ASIC synthesis in a 28 nm CMOS standard-cell library shows that the complete atrial detector core, integrating the Hjorth extractor and the hardware fully connected QNN, occupies on the order of 2×104μm2 and dissipates about 3 mW, with a critical-path delay of 7.08 ns. For the optimal 10–12-bit operating points, the synthesized core achieves per-inference energy in the range of 18.6–19.0 nJ (18,600–19,000 pJ) per classification, confirming its suitability for integration into wearable and IoMT ECG monitoring nodes. These results demonstrate that co-designed fixed-point Hjorth hardware and quantized DNNs can deliver a favorable trade-off between diagnostic performance, area, power, latency, and per-inference energy compared with existing MCU-, FPGA-, and ASIC-based ECG classifiers.