Hardware Acceleration of Fully Homomorphic Encryption: A Comprehensive Review of FPGA Implementations

  Although Fully Homomorphic Encryption (FHE) enables computation over encrypted data, its substantial computational and storage overhead remains a major obstacle to practical deployment. Among available hardware platforms, FPGAs offer a favorable balance of performance, flexibility, and energy efficiency, making them a promising option for FHE acceleration.

This paper presents a systematic review of FPGA-based FHE accelerators published between 2011 and 2025, with a focus on architectural design and performance characterization. To enable consistent analysis across heterogeneous implementations, we develop a unified framework that models FHE execution in terms of computation and data movement and supports a roofline-based interpretation of performance. Applying this framework to representative designs shows that accelerator performance is jointly shaped by arithmetic parallelism, memory bandwidth, data reuse, and communication overhead, and that the dominant bottleneck is therefore architecture-dependent. Designs with limited data reuse or inefficient key delivery may remain bandwidth-bound, whereas kernel-level implementations and carefully batched streaming architectures can become compute-bound. Based on these observations, we identify key challenges in memory hierarchy design, bandwidth utilization, communication efficiency, and scalability, and discuss future directions including algorithm–hardware co-design, communication-aware architectures, and application-specific acceleration. Overall, this review provides a unified perspective on the performance bottlenecks and design trade-offs of FPGA-based FHE accelerators and offers practical guidance for future architecture development.