Glass-on-Glass: Unlocking Opportunities for Packaging

We propose that by using SiO2, instead of polymers, as the dielectric for redistribution layers (RDLs) in packaging, significant technology advantages are enabled, and the common concerns of HVM cost-per-layer are overwhelmed by savings in time-to-market enabled by shorter cycles for development and reliability testing.  

SiO2 Enables Complexity: Polymer-based RDLs limit both lateral and vertical scaling.  Patterning is currently stuck at 1-2um line/space, well above predicted needs.  Similarly, polymer dielectrics limit vertical scaling, since beyond ~3 layers, they warp the wafer/panel package.  SiO2 immediately allows a 10x improvement in lateral scaling and 3x improvement in vertical scaling (foundries they routinely do 100nm L/S and 10 metal layers).  Another scaling / complexity improvement is that SiO2 enables hybrid bonding, which enables a 3-5x lateral scaling vs. microbumps.  

SiO2 Simplifies Devices-in-RDL: The drive towards hetero-integration is simultaneously driving a push for devices to be built between the chips on a package – either in the package substrate or in the RDL.  Resistors, capacitors and inductors and their combinations have already been built and optimized in the conventional damascene Cu/SiO2 BEOL of chips, so they can readily drop into a Cu/SiO2 RDL.  Re-developing these in Cu/Polymer, with its many inferior properties (line/space, tan-delta, quality factor, breakdown field, thermal expansion, moisture absorption) represents unnecessary effort.  

SiO2 Simplifies Photonics: The current drive to Optical Distribution Layers (ODLs) is greatly hampered when polymer is the dielectric.  The default waveguide (polymer-core / polymer-cladding), with its very poor Dn means waveguide dimensions and bend radii are huge (10x larger than on the PIC).  In contrast, an SiO2 RDL is an immediate win, since it enables high Dn structures (SiN-core / SiO2-cladding), exactly what is used in the PICs themselves.   

SiO2 Enables Reliability: Reliability is a major step in qualification of a package / product, and must be addressed up-front.  The reliability of the Cu/SiO2 material system is extremely well known, given its extensive use in the chip world.  In contrast, each polymer which is developed for packaging must be thoroughly tested.  Further, for high temperature applications, SiO2 is already known to perform reliably, while polymers decompose above 400C.

SiO2 Unlocks an Existing Infrastructure of People / Capability: To chipmakers, packaging is a different world – requiring different tooling, materials, processes, and personnel.  However, damascene Cu/SiO2 is well-known, and the barrier to entry drops significantly.  It is essentially continuing the BEOL, at fairly large dimensions.  The major hurdle now becomes learning the die-attach / final assembly – not simple, by any means, but much more realistic than attracting the talent and building a polymer RDL line.

SiO2 Enables Fast Time-to-Market: The need for smaller dimensions, and for off-chip devices will only increase.  It will be much easier to find solutions bring them to HVM quality when a) lateral and vertical scaling is not a limiter, b) known solutions in the same material system already exist (i.e. copy/paste from Logic, Memory or Photonics BEOL), and c) the creativity and talent which built those within-a-die solutions is turned loose to solve the die-to-die challenges.