Gate‐Induced Drain Leakage and Differential Resistance Optimization of Sub‐22‐nm Ferroelectric Negative Capacitance SOI FinFET Through Energy‐Band Tuning: Digital and Analog Performance Assessment

In this paper, a method to optimize the gate‐induced drain leakage (GIDL) and negative differential resistance (NDR) in a negative capacitance (NC) silicon on insulator (SOI) FinFET is proposed. Optimization is achieved by tuning the energy band to reduce the Miller capacitance. A four‐order improvement in GIDL is observed with the proposed method. The NDR of the device is optimized for the considered channel length of 20 nm, which is reflected as a 4% improvement in the voltage gain of the common‐source (CS) amplifier. The ferroelectric polarization is improved at the drain end of the channel. The improvements in GIDL and NDR are achieved with subthreshold swing (SS) intact around 57 mV/decade and a change in negative DIBL (N‐DIBL) of 3 mV/V. The switching performance comparison of the device is estimated with a CMOS Inverter for the considered drain‐doping profiles. It shows improvements in the rise and fall times and a two‐order‐of‐magnitude reduction in off‐state leakage. Analog/RF efficiency metrics, transconductance efficiency, and energy‐speed product are retained and improved, respectively.