Fractional-Order Memristive Chaotic Circuit: Dynamic Characterization and Dual-Platform Co-Simulation

Fractional-order modeling provides a flexible framework for extending memristive circuits with memory-dependent dynamics. This work develops a DC-driven memristive chaotic circuit within a unified fractional-order framework. The memristor is formulated with the Caputo derivative and discretized using Sayed’s scheme; the conventional first-order model is recovered at q=1, whereas 0<q<1 introduces nonlocal, history-dependent memory. The system dynamics are systematically analyzed through phase portraits, Lyapunov exponent spectra, bifurcation diagrams, C0 complexity, and the 0–1 test. Quantitative results show that the circuit exhibits a positive maximum Lyapunov exponent over the effective range q∈[0.78,1], with a representative value of LEmax=0.217 at q=0.98, and an averaged multi-scale C0 complexity of C0avg=0.12 in the parameter plane. Practical circuit-element bounds are set as L∈[1,10]H, C∈[0.1,0.14]F, and Vin∈[−5,−2]V, while the fractional-capacitor approximation is valid over f∈[0.01Hz,100Hz] with a magnitude error below 1.5dB. These results reveal that the fractional order q acts as a key bifurcation parameter regulating the system’s complexity and stability. To connect theoretical analysis with practical application, a dual-platform simulation framework is developed, utilizing MATLAB/Simulink for algorithmic verification and PSpice for circuit-level validation. An active emulator-based approach is proposed and validated at the circuit-simulation level. Operational amplifiers and analog multipliers are employed to implement the state equations by mapping the state variables to voltage signals. This study establishes a systematic methodology from mathematical modeling to circuit-level verification, emphasizing the significance of fractional-order control and emulation techniques in memristive chaotic systems.