Flip Chip Process Using the Cu-Sn-Cu Double-Pillar-Bump Bonding

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height and enable microelectronic packages to have better electrical and thermal characteristics. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. Conventional Cu pillar bump consists of a solder cap on a cylindrical Cu, and flip-chip bonding is accomplished by reflowing the solder cap on UBM of a substrate. Conventional Cu pillar bump technology may have several drawbacks such as necessity of deep photoresist patterning and severe UBM consumption. In this study, a flip-chip process using Cu-Sn-Cu double pillar-bump bonding has been investigated to avoid disadvantages of the conventional Cu pillar bump technology. Cu pillars with and without Sn caps were formed by electrodeposition, and Cu pillar bumps with Sn caps were flip-chip bonded to the Cu pillar bumps without Sn caps to form the Cu-Sn-Cu double-pillar-bump joints. Contact resistances and chip shear forces of the flip-chip specimens were measured with variation of the Sn-cap thickness. Thermal cycling reliability of the Cu-Sn-Cu double-pillar-bump joints was also evaluated.