Fine-Grained Structural Conflict Modeling for Compile-Time Instruction Scheduling on VLIW ASIPs

Application-specific instruction set processors (ASIPs) often employ specialized hardware to improve performance, but this introduces complexity in resource management and programming. Existing compiler solutions, including LLVM’s default schedulers, lack fine-grained structural conflict analysis for complex arithmetic logic unit (ALU) instructions, leading to suboptimal performance or runtime errors. This limitation becomes critical when targeting very long instruction word (VLIW) architectures with instruction fusion units that exhibit pipeline-stage-level resource contention. In this paper, we propose a compile-time instruction scheduling method that models sub-cycle resource usage and analyzes both data and structural dependencies at fine granularity. Unlike coarse-grained resource tables used in existing compilers, our approach tracks functional unit occupancy at the pipeline stage level, enabling precise detection of structural hazards in complex execution units. We implement this scheduler as a backend pass in the LLVM compiler framework and validate it on the Sayram VLIW processor for wireless communication. Experimental results show that our approach achieves 100% scheduling correctness while improving execution efficiency by 23% on average compared with in-order scheduling, with benefits up to 38% for highly parallel kernels such as PRACH, and reducing average running time by 66% compared with atomic execution.